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Rambus Announces Controllers with Zero-Latency IDE

Rambus Inc. released the Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 Controllers with zero-latency IDE modules, delivering “state-of-the-art” security and performance.

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Rambus is a premier chip and silicon IP provider that facilitates and speeds data processes. With its latest releases, the company will deliver the needed speed and security to solve the bandwidth bottleneck in the overall data center infrastructure.

The new CXL 2.0 and PCIe 5.0 controllers will feature zero-latency IDE (Integrity and Data Encryption) modules. The build-in IDE modules employ a 256-bit AES-GCM (Advanced Encryption Standard, Galois/Counter Mode) symmetric-key cryptographic block cipher.

In turn, chip designers and security architects can benefit from great functionality, especially on data center apps and high-performance computing.

Sean Fan, who serves the role of a Chief Operating Officer at Rambus, had this to say:

Successful enablement of CXL use models in data-intensive applications, such as memory sharing between processors and attached AI accelerators, requires security at ultra-low latency. Delivering controllers with zero-latency security is a testament of our ability to accelerate the development of CXL solutions through the recent acquisition of PLDA and showcases our unique position to provide integrated interface and security IP solutions.

The Compute Express Link (CXL) 2.0 Controller can enable load-store memory architectures and cache-coherent links with incredibly low latency. In turn, IDE monitors and protects against physical attacks on CXL and PCIe links.

According to Rambus, the new technologies will deliver performance at full 32 GT/s speed.

The Rambus CXL 2.0 Controller will include several key features. First, it will offer IDE security with zero latency for CXL.mem and CXL.cache.

It will also minimize the safety, financial, and brand reputation risks of a security breach. Most of all, it will do so with its robust protection from physical security attacks.

Furthermore, the pre-integrated IDE modules will reduce implementation risks and speed time-to-market.

At last, if you combine the controllers with Rambus CXL 2.0 and PCIe 5.0 PHYs, you will get complete CXL 2.0, and PCIe 5.0 interconnect subsystems.